1. Field of the Invention
The present invention relates to a semiconductor integrated circuit and a liquid crystal display device, and more particularly to a semiconductor integrated circuit for driving a source electrode of a TFT LCD panel and a liquid crystal display device comprised of a plurality of the semiconductor integrated circuits and the liquid crystal display panel.
2. Description of Related Art
FIG. 1 is a block diagram illustrating the configuration of a conventional liquid crystal display device (hereinafter, referred to as LCD device). In a LCD device 61, image data constituting an image signal and representing a degree of brightness of images at equal intervals on a logarithmic axis is employed as an input. A D.C. voltage varying in accordance with image data is generated based on a reference voltage within a LCD device and is supplied to a Liquid Crystal Display panel (LCD panel) 62 to display images. In this case, in the LCD panel 62, luminance is determined by a degree to which a backlight from a backside of the LCD panel is allowed to transmit through the LCD panel. In a generally used normally white LCD panel, Voltage-Transmittance (V-T) characteristics are specified such that transmittance becomes smaller in proportion to increase in input voltage. Accordingly, gamma correction is made by using the reference gray scale voltages Vγ and image data input according to the V-T characteristics of LCD panel to generate desired D. C. voltages, and then, the D. C. voltages are supplied to the LCD panel 62.
Data transmission from a display control circuit 63 to a signal line driving IC 65 is performed as follows. That is, image data corresponding to red (R), green (G), blue (B) and synchronizing data are inputted to the display control circuit 63, and the display control circuit 63 outputs image data DAT and signal line control signals CON1, CON2. Those signals are inputted to input terminals of individual signal line driving integrated circuits (hereinafter, referred to as signal line driving ICs) 65-1 to 65-m via metal lines formed on a board of a LCD device 1. That is, the input terminals of a plurality of signal line driving ICs 65 are connected to one output terminal of the display control circuit 63.
Configuration and operation of a conventional LCD device shown in FIG. 1 will be explained below. A LCD device 61 comprises a LCD panel 62, a display control circuit 63, a scanning line driving circuit 64 and m pieces of signal line driving ICs 65-1 to 65-m. The number of m pieces is determined by a ratio of the number of signal line inputs of the LCD panel 62 to the number of signal voltage outputs from the signal line driving ICs 65.
In the LCD panel 62, metal lines constituting a plurality of scanning lines are arranged as a row line in a longitudinal direction and metal lines constituting a plurality of signal lines are arranged as a column line in a lateral direction on a display plane, respectively. Pixel electrodes are disposed at all cross points between the scanning lines as a row line and the signal lines as a column line, and a thin film transistor (TFT) is disposed between a pixel electrode and a signal line corresponding to the pixel electrode, and further, a gate electrode of a TFT is connected to a scanning line corresponding to the TFT. Pixel electrodes corresponding to three primary colors, i.e., red (R), green (G), blue (B), are disposed in a horizontal direction to constitute a pixel and a first specific number of the pixels constructed as described above are disposed along the scanning line, and further, a second specific number of the pixel electrodes representing the same color are connected to each of the signal lines in a vertical direction, thereby constituting a pixel plane.
The display control circuit 63 generates image data DAT by rearranging, responsive to synchronizing data, the image data, which corresponds to red (R), green (G), blue (B) and consists of serial data, in accordance with arrangement of the pixels of the LCD panel with respect to individual scanning lines. In addition, the display control circuit 63 outputs the image data DAT to the signal line driving ICs 65-1 to 65-m while outputting, responsive to the synchronizing data, signal line control signals CON1, CON2 to the signal line driving ICs 65-1 to 65-m and scanning line control signal CON3 to a scanning line driving circuit 64, respectively. The signal line control signal CON1 actually consists of several signals which change at a relatively low rate such as a sift direction control signal R/L and latch signal STB. The signal line control signal CON2 actually consists of several signals which change at a relatively high rate such as a clock signal CLK and polarity inversion signal POL.
The scanning line driving circuit 64 outputs scanning signals to individual scanning lines every field period based on the scanning control signal CON3. The signal line driving IC 65 generates signals to which gamma correction is performed at every scanning period according to the V-T characteristics of LCD panel 2 by using the image data DAT and reference gray scale voltages Vγ supplied from the display control circuit 63 based on the signal line control signals CON1, CON2, and then, provides the signal to each signal line.
General operation of the LCD device 61 will be explained below. Image data is outputted from an image-drawing device such as a personal computer with respect to each color, i.e., red (R), green (G), blue (B), for example, in a serial form. The image data corresponding to each color is data consisting of bits corresponding to the number of gray scales of an image to be displayed, for example, is digital data consisting of six bits corresponding to 64 gray scales. In addition, the image-drawing device outputs vertical synchronizing signals as synchronizing data with respect to a display period of each field and horizontal synchronizing signals as synchronizing data with respect to a scanning period corresponding to each row line.
In the LCD device 61, the display control circuit 63 rearranges, responsive to the horizontal and vertical synchronizing data, the inputted image data corresponding to R, G, B with respect to individual scanning lines in such a manner that the order of R, G, B is repeated along a scanning line and then, outputs the image data rearranged in accordance with arrangement of pixels of the LCD panel 62 to the signal line driving ICs 65-1 to 65-m. Furthermore, the display control circuit 63 outputs the scanning line control signal CON3 to the scanning line driving circuit 64 and outputs the signal line control signals CON1, CON2 to the signal line driving ICs 65-1 to 65-m. 
The scanning line driving circuit 64 sequentially outputs scanning signals corresponding to one field to the individual scanning lines based on the scanning line control signal CON3 for every vertical scanning period. Receiving the scanning signal, each TFT whose gate electrode is connected to the scanning line turns on and an associated signal voltage is supplied from the signal line via the TFT to each pixel connected to the TFT being in an on-state.
Moreover, the signal line driving ICs 65-1 to 65-m receive the image data DAT and reference gray scale voltages Vγ corresponding to the individual colors, i.e., R, G, B, from the display control circuit 63 and perform gamma correction according to the V-T characteristics of the LCD panel 2 corresponding to individual colors to thereby obtain specific gamma value of the LCD panel and generate D. C. signal voltage outputs SO, and then, provide the signal voltage outputs to the associated signal lines of the LCD panel 62.
FIG. 2 illustrates an internal schematic diagram of the signal line driving IC 65. A signal line driving circuit chip 71 includes an internal circuit 14 comprised of a shift register, a data register, a latch circuit, a level shifter, a D/A converter (Digital-to-Analog converter) and a voltage follower output circuit. The signal line driving circuit chip 71 is housed within, for example, a TCP (Tape Carrier Package) and pads 22 of the signal line driving circuit chip 71 and terminals 23 of the package corresponding to the pads are connected to each other. In general, the number of the signal voltage outputs SO supplied from the signal line driving IC 65 to the LCD panel is very large and reaches about a few hundred, producing the following phenomenon. That is, the signal line driving circuit chip 71 is constructed such that one side of the chip 71 along which pads for outputting a signal voltage are disposed becomes far longer than another side thereof perpendicular to the one side when viewing the chip from a position vertical thereto. Terminals of the signal line driving IC 65 for outputting a signal voltage also are disposed in the IC 65 on a side thereof on which the pads for outputting a signal voltage are disposed. Since the number of inputs for receiving the image data DAT is relatively large, input pads of the signal line driving circuit chip 71 are disposed along a side thereof opposite the side thereof along which the pads for outputting a signal voltage are disposed and input terminals of the signal line driving IC 65 also are disposed so as to face the input pads of the chip 71. That is, as shown in FIG. 2, when viewing the IC from a position vertical thereto, generally, the input terminals are disposed, for example, on an upper side of the signal line driving IC 65 and the terminals for signal voltage output are disposed on a lower side thereof opposite the upper side.
In recent years, demand for development of a monitor screen capable of displaying a high resolution image and used for a medical industry or the like has been growing. For example, if images obtained by photographing the inside of human body using X ray were displayed on a high-resolution screen capable of presenting images nearly equal to those observed using a photograph, it becomes possible to observe delicate situation within a body from outside. To realize such high-resolution images on a display of a LCD device, the screen of the device has to be made to have a high density. Furthermore, in order to realize such a high density screen, pixels of the device has to be made fine and in a case where the size of a screen is the same as that of the conventional device, the LCD panel of the device houses a larger number of pixels therein. Since an amount of data increases in proportion to the number of pixels, when transmitting a large amount of image data, the data has to be transmitted at a higher rate. However, when producing high rate clock signals to transmit data at a higher rate, EMI (Electromagnetic Interference) occurs and the noise due to the EMI is imposed on the image data, adversely affecting quality of images to be displayed.
To solve the problems due to the EMI, Japanese Patent Application Laid-open No. 11-194748 as one of conventional techniques discloses the following technique. That is, in a case where the same amount of data is transmitted, clock frequency can be lowered by increasing the number of data buses and further, transmitting data in parallel. However, in the conventional technique disclosed in the above-described publication, the width of bus is required to be increased in proportion to increase in an amount of data, which increase is caused by higher resolution images, and therefore, a wiring area within the LCD device 61 increases, preventing the LCD device from reducing its volume. Since the LCD device is required to reduce its volume such that an outer frame of the LCD device 61 substantially becomes equal to that of the LCD panel 62, as well as to respond to the demand for higher resolution images, such technique requiring increase in a wiring area within the device cannot solve both problems described above.
A technique for providing a high rate interface while suppressing occurrence of EMI makes it possible to transmit data at a high rate from the display control circuit 63 to a plurality of the signal line driving ICs 65 without increase in the number of wiring connections. However, according to an ECL (Emitter Coupled Logic) interface, LVDS (Low Voltage Differential Signaling) interface or the like known as a conventional technique for providing a high rate interface while realizing low EMI, it is difficult to directly supply a signal from one transmitter to a plurality of receivers or it is required to most suitably and individually design the one transmitter depending on the number of the receivers and therefore, the conventional technique for providing a high rate interface has not easily been employed. To address such problems, Japanese Patent Application Laid-open No. 2001-53598 issued by the applicant of the present invention discloses a technique suitably applied for transmitting data at a high rate from one transmitter to a plurality of receivers. The applicant named this transmission method “CMADS (Current Mode Advanced Differential Signaling)” and proposed a LCD device employing this technique for transmitting image data and the like. In a CMADS circuit, since data transmission between the transmitter and receiver is performed by using a pair of differential signals each having an amplitude of about 100 to 200 mV, it becomes possible to transmit data while reducing the transmission of EMI noise to an extent equal to or greater than that could be achieved by using an ECL (Emitter Coupled Logic) interface, LVDS (Low Voltage Differential Signaling) interface or the like. Hereinafter, a transmission part of the CMADS circuit is referred to as a CMADS transmitter and a reception part thereof is referred to as a CMADS receiver, and a transmission line between the CMADS transmitter and CMADS receiver is referred to as a CMADS bus.
FIG. 3 illustrates an exemplified circuit diagram of the CMADS circuit disclosed in Japanese Patent Application Laid-open No. 2001-53598. A CMADS transmitter 81 includes MOS transistors 82 and 83 that alternately turn on depending on a binary input signal DI. A CMADS receiver 86 includes a MOS transistor 87 for supplying a specific current to a transmission line 84a when the MOS transistor 82 turns on and a MOS transistor 88 for supplying a specific current to a transmission line 84b when the MOS transistor 83 turns on. The CMADS receiver 86 outputs an inverted signal of a drain voltage DR of the MOS transistor 88 as a binary reception output signal DO. In the CMADS circuit, since the CMADS receiver 86 supplies an associated current, a plurality of CMADS receivers 86-1, 86-2, 86-3 can be connected in parallel with respect to one CMADS transmitter 81 via the transmission lines 84a, 84b, as shown in FIG. 3. Previously making on-resistance of each of the open drain MOS transistors 82 and 83 of the CMADS transmitter 81 sufficiently low requires no optimum design corresponding to the number of the receivers to be connected to the transmitter and thus, allows the CMADS circuit to operate without any problem.
In a case where a LCD device employs the CMADS circuit proposed by the applicant of this invention, the device can reduce its volume in the following manner. That is, the display control circuit 63 has the CMADS transmitter therein at the output portion thereof for outputting a high rate signal such as image data DAT and transmits the image data DAT onto a CMADS bus, and each of the signal line driving ICs 65-1 to 65-m has the CMADS receiver therein at an input portion thereof, thereby reducing the number of wirings used to transmit a high rate signal such as image data DAT. In the CMADS circuit, since data transmission at a rate of about four times that could be achieved by using a conventional CMOS circuit can be made, even taking into account the disadvantageous situation where the CMADS circuit employs a two-wire system, it is possible to reduce the number of bus lines to equal to or smaller than half the number of the conventional bus lines. This configuration of LCD device will be referred to as a second conventional technique, hereinafter. As described above, the applicant of the invention has realized a high-resolution and compact LCD device by applying the CMADS circuit to a LCD device. However, demand for a further miniaturized LCD device is growing and a high-resolution display device is strongly required to further reduce its volume.